1. Field of the Invention
The present invention relates to the field of design for testability of electronic circuits, and more specifically to a method and apparatus for achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques.
2. Related Art
Sequential scan techniques are often used to test integrated circuits. To support sequential scan techniques, integrated circuits are often designed to connect various sequential elements as a scan chain, i.e., the output of one element is connected as an input to the next element in the chain by a corresponding connecting path, with the first element in the chain being designed to receive bits of a input scan vector and the last element in the chain being designed to provide the output scan vector (“scan output”). The path starting from the point at which the input is received to the point at which the output is delivered is referred to as a scan chain path. Automatic test pattern generation (ATPG) is an example of one such sequential scan technique.
There is a general need to synchronize the data input (i.e., the bits of the scan vector) received from the prior sequential element with the clock signal driving the present sequential element. The synchronization is performed to ensure the setup and hold timings of the (present) sequential element are satisfied, as is well known in the relevant arts. The synchronization can be achieved either by delaying the clock input or the data input, as is also well known in the relevant arts. For conciseness, the description is substantially provided with respect to introducing delays in the data path, though the approaches would be applicable to introducing delays in the clock path as well.
One reason for the need for implementing delays to achieve synchronization in scan chains is that different connecting paths may provide different delays (e.g., due to the corresponding lengths of the connecting paths) in propagating the signal to the input of the next sequential element in the scan chain. To ensure that the signals arrive at corresponding sequential elements within desired the timing constraints, delay elements may be provided at least in the paths which otherwise provide small delays.
The determination and implementation of the delay magnitude on each path poses several challenges. For example, in a typical scenario, a designer designs an integrated circuit both for sequential scan testing (in a test mode) and to provide desired features (in a normal mode of operation) at a logical level (i.e., focusing on merely the logical connections between the elements) using various tools. A layout design is then generated from the logical design, with the physical layout determining the placement of various sequential elements and the length of the connecting paths.
A designer may need to modify the logical design to introduce additional delay elements if the prior physical layout is deemed not to satisfy the timing requirements. The layout design is then again checked for conformance with the timing requirements, and the logical design and layout generation are continued iteratively until a layout satisfies the desired synchronization requirements. Such iterative approach generally consumes time and resources (designer time, computational tools, etc.), and is therefore undesirable.
What is therefore needed is a method and apparatus which enables achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.